The development of a forward error correction (FEC) scheme suitable for use in 100-Gb/s communications systems and beyond is of considerable interest. Iteratively decodable codes, such as turbo-product codes (TPC) and LDPC codes are promising candidates as they provide improved bit-error ratio (BER) performance. Unfortunately they generally require soft bit reliabilities and consequently are difficult to implement for data rates above 100 Gb/s.